The present invention pertains to a method and device for compensating for clock drift in a coordinated computer system. More specifically, a method and device are provided for adjusting the decoding rate of encoded digital data to compensate for a mismatch between the clock of the device that is providing the data and the clock of the device that is decoding and rendering the data in a digital data transmission system.
In systems where digital data is encoded by an encoder, transmitted in packets of digital data, and decoded by a receiver, the encoder may receive data that includes digital samples of analog signals. Each digital sample may be a specific size (for example, 16 bits). A sampling rate represents the number of samples taken per unit of time (e.g., seconds, milliseconds). The encoder groups the samples into packets for transmission to a decoder.
The encoder places time stamp data in headers of the packets. The time stamp data represents the value of the encoder clock at various intervals, so that the decoding and encoding can be synchronized. In hardware decoders (for example, set-top boxes) the clock values represented in the time stamps are used to synchronize the decoder clock with the clock used to encode the data. Different time stamps may be used, for example, to indicate presentation time (the time at which a packet should be rendered (played), decode time (the time at which a packet should be decoded), and the reference value of the encoder system clock (at the time the data packet is created)). These time stamps are known as presentation time stamps (PTS), decoding time stamps (DTS), and system clock references (SCR).
In hardware decoder systems, the SCRs are used to synthesize a clock for the decoder, as described in Generic Coding of Moving Pictures and Associated Audio: Systems, Recommendation H.222.0, ISO/IEC 13818-1, Apr. 25, 1995 (xe2x80x9cMPEG 2 Specificationxe2x80x9d). Since the SCRs are the values of the encoder clock at various intervals, by adopting these values as the decoder clock, the encoder and decoder clocks are synchronized. This may be done, for example, with a phase lock loop. If the synthesized decoder clock and the encoder clock begin to become unsynchronized, the decoder clock is adjusted via the phase lock loop, which provides a negative feedback to the decoder clock. Since the decoder clock is a synthesized clock, and not simply a direct crystal clock input, it can be adjusted in this manner.
In systems that do not have a synthesized clock, however, this method of synchronization cannot be used. This may occur, for example, in a personal computer system employing an audio card to decode digital audio signals. Since many different components of personal computers may have their own clocks, there is no synthesized clock present in the system. Audio cards generally each contain their own crystal clocks, which cannot be adjusted to accomplish synchronization with another clock. Another method, for example a software method, is therefore needed to compensate for the fact that the encoder clock and the decoder clock in, for example, a personal computer system, may not be synchronized.
In one embodiment of the present invention, a method and device are provided for compensating for clock skew in a coordinated computer system adapted to transmit a series of digital data packetsxe2x80x94each digital data packet including a digital data samplexe2x80x94from an encoder to a decoder, comprising calculating a drift metric to represent the clock skew between an encoder clock and a decoder clock; modifying a time stamp of a digital data packet based on the drift. metric; and performing a sample rate conversion to adjust the playback rate of digital data.